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Product Brief
PE42632 Flip Chip
SP6T UltraCMOSTM 2.70 V Switch 100 - 3000 MHz, 50
Figure 1. Functional Diagram
Features
* Three pin CMOS logic control with
V1 V2 V3
CMOS Control/ Driver and ESD
TX1
* * * * * * *
TX2
integral decoder/driver Low TX insertion loss: 0.55 dB at 900 MHz, 0.60 dB at 1900 MHz TX - RX Isolation of 38 dB at 900 MHz, 31 dB at 1900 MHz Low harmonics: 2fo = -90 dBc and 3fo = -82 dBc 1500 V HBM ESD tolerance all ports 41 dBm P1dB, TX paths No blocking capacitors required RoHS compliant lead-free solder balls
RX4
RX3
RX2
RX1
Figure 2. Die Top View
GND ANT VDD 12 13 14 1 TX1
Product Description
The PE42632 is a HaRPTM-enhanced SP6T RF Switch developed on the UltraCMOSTM process technology. This 50 switch addresses the specific design needs of the Quad-Band GSM Handset Antenna Switch Module Market. On-chip CMOS decode logic facilitates three-pin low voltage CMOS control. High ESD tolerance of 1500 V at all ports, no blocking capacitor requirements and on-chip SAW filter over-voltage protection devices make this the ultimate in integration and ruggedness. Peregrine's HaRPTM technology enhancements deliver high linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOSTM process, providing performance superior to GaAs with the economy and integration of conventional CMOS.
V1
11
15
GND
2
GND
V2
10
16
GND
3
TX2
V3
9
PE42632 Die
GND
8
7 RX4
6 RX3
5 RX2
4
RX1
Figure 3. Package Type: Flip Chip
Document No. 70-0226-01 www.psemi.com Contact sales@psemi.com for full version of datasheet
(c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 4
PE42632
Product Brief
Table 1. Electrical Specifications @ +25 C, VDD = 2.5 - 2.8 V (ZS = ZL = 50 )
Parameter
Operational Frequency ANT - TX - 850 / 900 MHz ANT - TX - 1800 / 1900 MHz ANT - RX - 850 / 900 MHz ANT - RX - 1800 / 1900 MHz TX - RX - 850 / 900 MHz TX - RX - 1800 / 1900 MHz TX - TX - 850 / 900 MHz TX - TX - 1800 / 1900 MHz 850 / 900 MHz 1800 / 1900 MHz 35 dBm TX Input - 850 / 900 MHz 33 dBm TX Input - 1800 / 1900 MHz 35 dBm TX Input - 850 / 900 MHz 33 dBm TX Input - 1800 / 1900 MHz 50% Control Logic to 90% RF
Conditions
Typical
100-3000 0.55 0.6 0.9 1.15 38 31 31 26 23 22 -90 -89 -82 -80 1
Units
MHz dB dB dB dB dB dB dB dB
Insertion Loss1
Isolation
Return Loss 2nd Harmonic2,3 3rd Harmonic2,3 Switching Time4 Notes:
dB dBc dBc s
1. Insertion loss specified with optimal ANT impedance matching. 2. Measured in Pulsed Wave Mode. 3. Assumes RF input duty cycle of 50% and 4620 s, measured per 3GPP TS 45.005 4. Power on any port must not exceed +20 dBm during switching event.
Table 2. Operating Ranges
Parameter
Temperature range VDD Supply Voltage IDD Power Supply Current (VDD = 2.75 V) TX input power5 (VSWR 3:1) 824-915 MHz TX input power (VSWR 3:1) 1710-1910 MHz
5
Table 3. Absolute Maximum Ratings
Min
-40 2.5 2.70 13
Symbol
TOP VDD IDD
Typ
Max
+85 2.8 20 +35
Units
C V A
Symbol VDD VI TST TOP
Parameter/Conditions Power supply voltage Voltage on any DC input Storage temperature range Operating temperature range TX input power (50 )6,7 824-915 MHz TX input power (50 )6,7 1710-1910 MHz RX input power (50 )7 TX input power (VSWR = ( :1)6,7 824-915 MHz TX input power (VSWR = ( :1)6,7 1710-1910 MHz ESD Voltage (HBM, MIL_STD 883 Method 3015.7) ESD Voltage (MM, JEDEC, JESD22-A114-B)
Min -0.3 -0.3 -65 -40
Max 4.0 VDD+ 0.3 +150 +85 +38 +36 +23 +35 +33 1500 100
Units V V C C
PIN +33 PIN VIH VIL 0.7 x VDD 0.3 x VDD +20
dBm
PIN (50 )
dBm V V
dBm
RX input power5 (VSWR =1:1) Control Voltage High Control Voltage Low
dBm dBm V V
PIN ( :1)
Note:
5. Assumes RF input period of 4620 s and duty cycle of 50%. VESD
Notes:
6. Assumes RF input period of 4620 s and duty cycle of 50%. 7. V DD within operating range specified in Table 2.
Part performance is not guaranteed under these conditions. Exposure to absolute maximum conditions for extended periods of time may adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage.
(c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 4 Document No. 70-0226-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet
PE42632
Product Brief
Table 4. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note:
Figure 4. Pad Configuration (Top View)
Description
GND ANT VDD 12 13 14 1 TX1
Pin Name
TX18 GND TX28 RX18 RX28 RX3
8
RF I/O - TX1 TX Ground RF I/O - TX2 RF I/O - RX1 RF I/O - RX2 RF I/O - RX3 RF I/O - RX4 RX Ground Switch control input, CMOS logic level Switch control input, CMOS logic level Switch control input, CMOS logic level Supply DC Ground RF Common - Antenna DC Ground DC Ground
V1
11
15
GND
2
GND
V2
10
16
GND
3
TX2
RX48 GND V3 V2 V1 VDD GND ANT8 GND GND
V3
9
PE42632 Die
GND
8
7 RX4
6 RX3
5 RX2
4
RX1
Table 5. Truth Table
Path
ANT - TX1 ANT - TX2 ANT - RX1 ANT - RX2 ANT - RX3 ANT - RX4
V3
0 0 1 0 1 0
V2
1 0 1 1 0 0
V1
1 1 0 0 0 0
8. Blocking capacitors needed only when non-zero DC voltage present
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
Table 6. Ordering Information
Order Code PE42632DTI PE42632DBI EK-42632-01 Description PE42632-DIE-D PE42632-DIE-400G PE42632-DIE-1H Package Bumped Wafer on Film Frame Die in Waffle Pack Evaluation Kit Shipping Method Wafer (Gross Die / Wafer Quantity) 400 Dice / Waffle Pack 1/ box
Document No. 70-0226-01 www.psemi.com Contact sales@psemi.com for full version of datasheet
(c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 4
PE42632
Product Brief
Sales Offices
The Americas Peregrine Semiconductor Corporation
9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499
Peregrine Semiconductor, Asia Pacific (APAC)
Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940
Europe Peregrine Semiconductor Europe
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Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
Space and Defense Products
Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
(c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 4
Document No. 70-0226-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet

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